1. Field of the Invention
The present invention generally relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus having a large-size bus connection (super connection) which attention is currently focused on.
2. Description of the Related Art
A large-size bus connection (supper connection) is a wiring technology that employs a large-size bus wiring layer having a comparatively large width in a range of 5 ▪ ▪ ▪ to 10 ▪ ▪. The large-size bus connection is expected to make it possible to provide a high-speed operation of semiconductor apparatus with low power consumption.
The large-size bus connection has the following advantages over a normal-size bus connection that is formed in a conventional semiconductor apparatus through micromachining:
1) it provides a small electrical resistance because the width of the wiring layer is large,
2) it provides a small parasitic capacity because the inter-layer distance between the bulk and the insulating layer and the wiring intervals of the large-size bus connection are large, and
3) it is suited for a high-speed operation of semiconductor devices because the time constant of the large-size bus is very small.
The packaging areas of semiconductor devices have been reduced on a yearly basis, and high-density implementation methods, such as ball-grid array (BGA), have been developed. When the BGA method is used, the bumps are arrayed on the surface of a semiconductor chip. The re-wiring method is provided to connect the bumps with the integrated circuit of the semiconductor chip. The re-wiring method employs a wiring layer including a pattern of wiring on the resin layer, such as polyimide resin, which is provided on the chip surface. The wiring layer, used in the re-wiring method, has a relatively large width, and it may be considered the large-size bus connection.
Further, a multi-chip semiconductor apparatus in which a logic device and a memory device coexist is known. For example, in the multi-chip semiconductor apparatus, the memory chip is overlaid onto the logic chip, and the connection of the memory device and the logic device is established by using the large-size bus wiring layer in the rewiring method, such as the bumps or the like. The large-size bus connection is provided to connect together the I/O (input/output) devices of the two chips.
Each of the logic chip and the memory chip includes a plurality of blocks, and each block contains the internal circuits. The internal circuits of the blocks and the I/O device are interconnected by an internal bus of each of the logic chip and the memory chip. For the purpose of connection of various circuits, the internal bus of each chip in the multi-chip semiconductor apparatus has a relatively large length of the wiring. In a conventional multi-chip semiconductor apparatus, the internal buses of the chips are a normal-size bus that is formed by using a micromachining process, although the length of the wiring is increasing as the degree of integration grows. The parasitic capacity of the internal buses in the conventional multi-chip semiconductor apparatus is increased due to the use of the normal-size bus connection, which will lower the operating speed of the apparatus and increase the power consumption of the apparatus. Hence, it is difficult for the conventional multi-chip semiconductor apparatus to provide a high-speed operation with low power consumption if the degree of integration of the circuits in the chip grows.